Circuit Including a Field-Effect Transistor and a Bipolar Transistor

ABSTRACT

A circuit can include a field-effect transistor having a body, a drain, a gate, and a source. In an embodiment, the circuit can further include a bipolar transistor having a base and a collector, wherein the collector of the bipolar transistor is coupled to the body of the field-effect transistor; and the drain of the field-effect transistor is coupled to the base of the bipolar transistor. In another embodiment, the circuit can include a diode having an anode and a cathode, wherein the source of the field-effect transistor is coupled to the anode of the diode, and the gate of the field effect transistor is coupled to the cathode of the diode. In another aspect, an electronic device can include one or more physical structures that correspond to components within the circuits.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of and claims priority under 35 U.S.C.§ 120 to U.S. patent application Ser. No. 15/666,814 entitled “CircuitIncluding a Field-Effect Transistor and a Bipolar Transistor and anElectronic Device Including a Ring Suppression Structure” by Gary HorstLoechelt, filed Aug. 2, 2017, which is assigned to the current assigneehereof and incorporated herein by reference in its entirety.

FIELD OF THE DISCLOSURE

The present disclosure relates to circuits and electronic devices, andin particular, to circuits including field-effect transistors andbipolar transistors, and to electronic devices that include field-effectand bipolar transistors.

RELATED ART

Ringing is a problem in power conversion circuits. Switching of largecurrents reacts with parasitic inductance in the circuit to createpotentially large voltage overshoots. Ringing may occur during reverserecovery of a metal-oxide-semiconductor field-effect transistor bodydiode or in hard switching circuit topologies. Further improvements toaddress ringing issues are desired.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments are illustrated by way of example and are not limited in theaccompanying figures.

FIG. 1 includes a schematic diagram of a circuit that can be used forring suppression in accordance with an embodiment.

FIG. 2 includes illustrations of portions of physical structures withthe circuit of FIG. 1 overlaid onto the portions of the physicalstructures.

FIGS. 3 and 4 include illustrations of cross-sectional and top views ofa portion of a workpiece including a substrate, a semiconductor layer,and doped regions.

FIGS. 5 and 6 include illustrations of cross-sectional and top views ofthe workpiece of FIGS. 3 and 4 after forming another semiconductor layerand doped regions.

FIGS. 7 and 8 include illustrations of cross-sectional views of theworkpiece of FIGS. 5 and 6 after forming pillars and trenches.

FIGS. 9 and 10 include illustrations of cross-sectional views of theworkpiece of FIGS. 7 and 8 after forming a doped semiconductor layerwithin the trenches.

FIGS. 11 and 12 include illustrations of cross-sectional views of theworkpiece of FIGS. 9 and 10 after forming a gate dielectric layer,filling the trenches and forming gate electrodes and body regions.

FIGS. 13 and 14 include illustrations of cross-sectional views of theworkpiece of FIGS. 11 and 12 after forming source regions and recessingthe gate electrodes.

FIGS. 15 and 16 include illustrations of cross-sectional views of theworkpiece of FIGS. 13 and 14 after forming a substantially completedphysical structure.

FIG. 17 includes an illustration of a cross-sectional view of a portionof a comparative example of power transistor without a ring suppressionstructure and a plot of simulated voltage and current as a function oftime during a switching operation.

FIG. 18 includes an illustration of a plot of simulated voltage andcurrent as a function of time during a switching operation for thesuppression-side structure as described and illustrated in FIGS. 15 and16.

Skilled artisans appreciate that elements in the figures are illustratedfor simplicity and clarity and have not necessarily been drawn to scale.For example, the dimensions of some of the elements in the figures maybe exaggerated relative to other elements to help to improveunderstanding of embodiments of the invention.

DETAILED DESCRIPTION

The following description in combination with the figures is provided toassist in understanding the teachings disclosed herein. The followingdiscussion will focus on specific implementations and embodiments of theteachings. This focus is provided to assist in describing the teachingsand should not be interpreted as a limitation on the scope orapplicability of the teachings. However, other teachings can certainlybe utilized in this application.

In the following description, the terms “intrinsic”, “lightly-doped”,“moderately-doped”, and “heavily-doped”, and “degenerate” are employedto indicate relative degrees of doping. These terms are not intended toindicate definitive numerical ranges, but rather to indicate relativedopant concentration levels. Approximate ranges whose upper and lowerextremes may be allowed to vary by a factor of 4 in either direction.For example, with silicon, the term “intrinsic” can indicate a dopantconcentration of 10¹⁴ atoms/cm³ or less, “lightly-doped” can indicate aconcentration in the range between 10¹⁴ and 10¹⁶ atoms/cm³,“moderately-doped” can indicate a concentration in the range of 10¹⁶ to10¹⁸ atoms/cm³, inclusive, and “heavily-doped” can indicate aconcentration in the range of 10¹⁸ to 10²⁰ atoms/cm³. “Degenerate”indicates a doping level sufficient to provide an ohmic (non-rectifying)connection with a metal contact (generally greater than 10²⁰ atoms/cm³).Note that for semiconductors other than silicon, these ranges may vary.

The terms “comprises,” “comprising,” “includes,” “including,” “has,”“having,” or any other variation thereof, are intended to cover anon-exclusive inclusion. For example, a method, article, or apparatusthat comprises a list of features is not necessarily limited only tothose features but may include other features not expressly listed orinherent to such method, article, or apparatus. Further, unlessexpressly stated to the contrary, “or” refers to an inclusive-or and notto an exclusive-or. For example, a condition A or B is satisfied by anyone of the following: A is true (or present) and B is false (or notpresent), A is false (or not present) and B is true (or present), andboth A and B are true (or present).

Also, the use of “a” or “an” is employed to describe elements andcomponents described herein. This is done merely for convenience and togive a general sense of the scope of the invention. This descriptionshould be read such that the plurals include one or at least one and thesingular also includes the plural, unless it is clear that it is meantotherwise. For example, when a single item is described herein, morethan one item may be used in place of a single item. Similarly, wheremore than one item is described herein, a single item may be substitutedfor that more than one item.

The use of the word “about”, “approximately”, or “substantially” isintended to mean that a value of a parameter is close to a stated valueor position. However, minor differences may prevent the values orpositions from being exactly as stated. Thus, differences of up to tenpercent (10%) for the value are reasonable differences from the idealgoal of exactly as described.

Unless otherwise defined, all technical and scientific terms used hereinhave the same meaning as commonly understood by one of ordinary skill inthe art to which this invention belongs. The materials, methods, andexamples are illustrative only and not intended to be limiting. To theextent not described herein, many details regarding specific materialsand processing acts are conventional and may be found in textbooks andother sources within the semiconductor and electronic arts.

A circuit and an electronic device can be configured to reduce theeffects of ringing when a transistor switches between on and off states.Power transistors allow relatively high current to pass when on and canhave significant ringing when the transistor is switched from the onstate to the off state. A ring suppression structure may be incorporatedinto a circuit and an electronic device to help control energydissipation and reduce the amount of voltage overshoot and undershootand to reduce the time needed to be with 5% of the targeted voltage. Ina particular embodiment, a bipolar transistor and a junctionfield-effect transistor can be serially connected and controlled by thedrain voltage of the power transistor.

In an aspect, a circuit can include a field-effect transistor having abody, a drain, a gate, and a source. In an embodiment, the circuit canfurther include a bipolar transistor having a base and a collector,wherein the collector of the bipolar transistor is coupled to the bodyof the field-effect transistor; and the drain of the field-effecttransistor is coupled to the base of the bipolar transistor. In anotherembodiment, the circuit can include a diode having an anode and acathode, wherein the source of the field-effect transistor is coupled tothe anode of the diode, and the gate of the field effect transistor iscoupled to the cathode of the diode.

In another aspect, an electronic device can include a substrateincluding a semiconductor material, a first trench, and a second trenchspaced apart from the first trench, and a ring suppression structuredisposed between the first and second trenches. The ring suppressionstructure can include a first doped region overlying the substrate andhaving a first conductivity type; a second doped region overlying thefirst doped region and having a second conductivity type opposite thatof the first conductivity type; and a third doped region overlying thesecond doped region and having the first conductivity type.

In a further aspect, an electronic device can include a first structureand a second structure. The first structure can include a first dopedregion having a first conductivity type; a second doped region overlyingthe first doped region and having a second conductivity type oppositethe first conductivity type; and a third doped region overlying thesecond doped region and having the first conductivity type. The secondstructure can include a fourth doped region having the firstconductivity type and coupled to the first doped region of the firststructure.

The circuits and electronic devices will be understood after reading thespecification in light of the figures. After reading this specification,skilled artisans will appreciate that embodiments described herein areexemplary and do not limit the scope of the present invention, asdefined in the appended claims.

FIG. 1 includes an exemplary circuit to aid in ring suppression for apower transistor. In an embodiment, the power transistor is an insulatedgate field-effect transistor (IGFET). As will be described later in thisspecification, the left-hand side of FIG. 1 includes a ring suppressionportion of the circuit, and the right-hand side of the FIG. 1 includes acontact portion of the circuit and provides proper biasing of a buriedregion within the trench. For purposes of this specification, theleft-hand side of FIG. 1 is referred to as the suppression side, and theright-hand side of FIG. 1 is referred to as the contact side. A bipolartransistor is the only component difference between suppression-side andcontact-side portions of the circuit.

Referring to the circuit, a source terminal 110 is coupled to sourcesand bodies of the power transistors 102 and 103, a collector of abipolar transistor 122, and a drain of a contact-side junctionfield-effect (JFET) 125. A gate terminal 120 is coupled to the gates ofthe power transistors 102 and 103. An emitter of the bipolar transistor122 is coupled to a drain of a suppression-side JFET 124. A drainterminal 130 is coupled to drains of the power transistors 102 and 103,a base of the bipolar transistor 122, gates of the suppression-side andcontact-side JFETs, 124 and 125, and electrodes of charge storageelements. The other electrodes of the charge storage elements arecoupled to sources of the suppression-side and contact-side JFETs. In anembodiment, the power transistors 102 and 103 are n-channel IGFETs, thebipolar transistor 122 is a PNP bipolar transistor, the JFETs 124 and125 are p-channel JFETs, and the charge storage elements are pn junctiondiodes 132 and 133.

In a particular embodiment, a resistor 142 is coupled between thecollector of the bipolar transistor 122 and the source terminal, aresistor 143 is coupled between the drain of the contact-side JFET 125and the source terminal, and a resistor 148 is coupled between thesources of the suppression-side and contact-side JFETs 124 and 125.

In a particular embodiment, many of the previously-described couplingscan be in the form of electrical connections at nodes. In a moreparticular embodiment, the drain terminal 130, the drains of the powertransistors 102 and 103, the base of the bipolar transistor 122, thegates of the suppression-side and contact-side JFETs 124 and 125, andcathodes of the pn junction diodes 132 and 133 are electricallyconnected to each other at a node. The gate terminal 120 is electricallyconnected to the gates of the power transistors 102 and 103 at anothernode. The source terminal 110, the sources of the power transistors 102and 103, and terminals of resistors 142 and 143 are electricallyconnected to each other at a further node. The other terminal of theresistor 142 is electrically connected to the collector of the bipolartransistor 122 at still another node; the emitter of the bipolartransistor 122 is electrically connected to the drain of thesuppression-side JFET 124 at yet another node; and the source of thesuppression-side JFET 124, the anode of the suppression-side pn junctiondiode 132, and a terminal of the resistor 148 are electrically connectedto one another at a further node. The other terminal of resistor 148 iselectrically connected to the source of the contact-side JFET 125 andthe anode of the contact-side pn junction diode 133; and the drain ofthe contact-side JFET 125, and the other terminal of resistor 143 areelectrically connected to one another at another node.

In the previously described circuit, not all of the components arerequired. For example, a different type of contact structure may be madeto a semiconductor feature that includes the current-carrying portion ofthe suppression-side JFET 124 and emitter of the bipolar transistor 122.In such an embodiment, the contact-side JFET 125, the contact-side pnjunction diode 133, resistors 143 and 148, or any combination thereofmay not be present. In another example, the suppression-side JFET 124 orthe contact-side JFET 125 may be replaced by resistors.

FIG. 2 includes the circuit of FIG. 1 overlaid onto an exemplaryphysical structure, so that components in the circuit diagram arecorrelated to portions of the physical structure. All of the portions ofthe workpiece illustrated in FIG. 1 can be formed within the same trenchor different trenches. Thus, the illustrations of the structures in FIG.2 can be at different portions within the same trench or be withindifferent trenches. Additional power transistor structures can be formedin other trenches. Source regions of the power transistor structures canbe connected to each other, gate electrodes of the power transistorstructures can be connected to each other, and drain regions of thepower transistor structures can be connected to each other. Thecorrelation between the circuit and physical structure will become moreapparent with the process description in forming the physical structure.

A process of forming an electronic device that includes the circuit isdescribed below. After reading this specification in its entirety,skilled artisans will appreciate that other processes and electronicdevices can be formed that include at least portions of thepreviously-described circuit. In the description of the process, someoperations are well known are at not described; however, after readingthis specification, skilled artisans will understand such operations canbe performed when desired or needed. For example, before forming a dopedregion within a layer, a screen oxide layer may be formed to reduce theeffects of implant channeling, particularly when boron ions are used arethe species during implant. The screen oxide layer may or may not beremoved. Further, an anneal may be formed after a doping with one or aplurality of dopants. Thus, the anneal may be performed as the nextoperation or may be deferred until later in the process flow. Stillfurther, an oxide layer may be grown and removed at one or moreparticular points in the process to smooth an exposed surface of asemiconductor material.

FIG. 3 includes an illustration of a workpiece 300 having a partiallyformed electronic device. The workpiece 300 comprises a semiconductorsubstrate 302, a semiconductor layer 322, doped regions 324, and a dopedregion 326 that is buried within the semiconductor layer 322. Thesubstrate 302 can be a heavily doped semiconductor material, such asn-type silicon, and has a resistivity in a range of 1 milliohm-cm to 3milliohm-cm.

The semiconductor layer 322 is deposited over the substrate 302. In anembodiment, the semiconductor layer 322 is an epitaxially grown siliconlayer. In a particular embodiment, the semiconductor layer 322 has athickness that is in a range of 1.5 microns to 5 microns and has ann-type dopant, such as phosphorus, at a concentration of at most 1×10¹⁶atoms/cm³.

The doped regions 324 will be parts of a drain region for the powertransistor and gates of the JFETs and will subsequently be connectedwith the substrate 302. Thus, the substrate 302 and the doped regions324 have the same conductivity type. The doped region 324 can beselectively formed along the upper surface of the semiconductor layer322. In an embodiment, the doped region 324 can be formed by implantingarsenic ions (As⁺). The doped region 324 has peak dopant concentrationsin a range of 1×10¹⁸ atoms/cm³ to 1×10²⁰ atoms/cm³ at a depth of 0.1micron to 0.5 microns below the surface of the semiconductor layer 322.

The doped region 326 will be parts of the anodes of the pn junctiondiodes and source regions of the JFETs. The doped region 326 has aconductivity type opposite that of the substrate 302 and the dopedregions 324. The doped region 326 is formed such that the peak dopantconcentration is approximately half way between the substrate 302 andthe location of the peak concentration of the doped region 324. Thedoped region 326 can be formed with boron ions (e.g., B⁺ or B³⁺). Thedoped region 326 has a peak dopant concentration in a range of 5×10¹⁶atoms/cm³ to 1×10¹⁸ atoms/cm³.

FIG. 4 includes a top view of the workpiece at this point in the processflow. The doped region 324 covers most of the workpiece. Other portionscorrespond to areas where the doped region 326 is not covered by thedoped region 324. Such uncovered portions correspond to locations wherebase regions (wider areas) of the bipolar transistor structures and thecontact-side structures (narrower areas) will be formed.

FIG. 5 includes a cross-sectional view after forming a semiconductorlayer 522 and doped regions 524 that will include base regions for thetransistor structures. The semiconductor layer 522 is deposited over thedoped region 324 and the semiconductor layer 322. In an embodiment, thesemiconductor layer 522 is an epitaxially grown silicon layer. In aparticular embodiment, the semiconductor layer 522 has a thickness is ina range of 1.5 microns to 5 microns and has an n-type dopant, such asphosphorus, at a concentration of at most 1×10¹⁶ atoms/cm³.

Before forming the doped regions 524, a mask is formed over theworkpiece, as illustrated in FIG. 6, such that a masking member coverslocations where the doped regions 524 will not be formed. A portion ofthe masking member covers the contact-side structures as previouslydescribed with respect to FIG. 4. The doped regions 524 have aconductivity type that is the same as the substrate 302 and doped region324 and opposite the doped region 326. The uncovered areas are implantedwith ions of an n-type dopant, such as arsenic ions (As⁺). In aparticular embodiment, the doped regions 524 have a peak depth in arange of 0.05 micron to 0.5 micron and in a range of 1×10¹⁷ atoms/cm³ to5×10¹⁸ atoms/cm³. The mask is removed after forming the doped regions524.

A relatively thick semiconductor layer can be epitaxially grown over thedoped regions 524 and other portions of the semiconductor layer 522. Thethickness may depend on the normal operating voltage of the transistorstructures, with a relatively thicker semiconductor layer being used forrelatively higher normal operating voltages and a relatively thinnersemiconductor layer being used for relatively lower normal operatingvoltages. The semiconductor layer may be doped with an n-type dopant, ap-type dopant, or be undoped. If the semiconductor layer is doped, thedopant concentration will be at most 1×10¹⁶ atoms/cm³.

A hard mask layer 702 is formed over the semiconductor layer, and thesemiconductor layer is patterned to form pillars 722 and define trenches724 between the pillars 722, as illustrated in FIGS. 7 and 8. FIG. 7includes the lengths (vertical direction) of the pillars 722 and theentire depths of the trenches 724, and FIG. 8 include an enlargedportion near the bottoms of one of the pillars 722 and trenches 724. Thetrenches 724 extend through the relatively thick semiconductor layer,the doped regions 524, the semiconductor layer 522, the doped regions324, and part of the semiconductor layer 322 (not labeled in FIGS. 7 and8). In the embodiment illustrated, a remaining portion of thesemiconductor layer 322 between the trench bottoms and the substrate 302is in a range of 1 micron to 2 microns thick. In another embodiment, thebottom of the trenches may extend to the substrate 302. Each of thepillars 722 and trenches 724 has a width in a range of 1.1 microns to5.0 microns. The illustrations in FIGS. 7 and 8 correspond to thesuppression-side structure. The pillars of the contact-side structurecan be narrower, substantially the same as, or wider than the pillars722, and the trenches of the contact-side structure can be narrower,substantially the same as, or wider than the trenches 724. In aparticular embodiment, the pillars of the contact-side structures arenarrower than the pillars 722 and may be as narrow as 0.5 micron, andthe trenches of the contact-side structures are substantially the sameat the trenches 724. The pillars for the contact-side structures wouldhave the same composition as the pillars 722 except that the dopedregions 524 are not present.

Charge compensation regions 846 are formed along sidewalls of thepillars 722. In an embodiment, the charge compensation regions 846 areformed using ion implant. In one embodiment, boron (B⁺) ions areimplanted to a total dose in a range of 1.0×10¹³ ions/cm² to 4.0×10¹³ions/cm² at an energy in a range of 25 to 40 keV with a 7° to 10° tiltangle. In a particular embodiment, the total dose can be introduced asfour implants at ¼ of the total dose with a 90° rotation of thesubstrate 302 between the implants. The effective implant and depth maybe reduced when a screen oxide layer is present. Because of the smallangle between the ion implant and the trench sidewall, the ion implantalong the sidewall would be equivalent to an ion implant perpendicularto the surface with an effective dose in the pillars 722 along thesidewalls of the pillars 722 in a range of 3.0×10¹² ions/cm² to 7.0×10¹²ions/cm². In subsequent thermal diffusion steps, the dopant will diffuseto create the charge compensation regions, and, in a particularembodiment, extend throughout the widths of the pillars 722 betweenadjacent trenches 724 and above the doped regions 524.

Sidewalls spacers (not illustrated) can be formed in the trenches 724 toprotect sidewalls of the pillars 722 and expose portions of thesemiconductor layer 322 at the bottoms of the trenches 724. If needed ordesired, some of the semiconductor layer 322 along the bottoms oftrenches 724 may be etched to remove dopant from the charge compensationimplant. In an embodiment, no more than 0.4 micron of the semiconductorlayer 322 is removed.

In another embodiment, the charge compensation regions can be formedfrom a deposited doped semiconductor layer. The semiconductor layer canbe formed by epitaxially growing a p-type semiconductor layer alongsidewalls of the pillars 722. The semiconductor layer may or may notinclude a thin buffer layer of intrinsic semiconductor material.Portions of the semiconductor layer are etched to remove thesemiconductor layer along an uppermost surface of the workpiece andalong the bottoms of the trenches 724. As before, dopant in theremaining portions of the p-type semiconductor layer can be diffusedinto the pillars 722.

The bottoms of the trenches 724 can be doped to allow a lower resistanceconduction path to the substrate 302. In an embodiment, the dopedregions 824 are formed within the semiconductor layer 322 adjacent tothe bottoms of the trenches 724. The doped regions 824 have the sameconductivity type as the doped region 324 and the substrate 302. Thepeak dopant concentration within the doped regions 824 can be greaterthan 2×10¹⁷ atoms/cm³. An anneal can be performed to drive the dopantsto achieve the doped regions and other features as illustrated in FIGS.7 and 8. The contact-side structures will have the same construction andbe formed using the same process sequence except that the doped regions524 are not present.

FIGS. 9 and 10 include cross-sectional views of the full height of thestructure and an enlarged view near the top of the structure afterforming a doped semiconductor layer 924 that can be a chargecompensation layer for the structure. In an embodiment, the dopedsemiconductor layer 924 can be epitaxially grown from exposed portionsof the semiconductor material along sidewalls of the pillars 722 andwithin the trenches 724. If a non-selective epitaxy process is used, theportion of the doped semiconductor layer 924 formed over the hard masklayer 702 will be polycrystalline. If a selective epitaxy process isused, there will be substantially no semiconductor layer formed over thehard mask layer 702. In an embodiment, the doped semiconductor layer 924has a thickness in a range of 0.5 microns to 1.2 microns. In aparticular embodiment, the doped semiconductor layer 924 includes abuffer film of 40 nm to 120 nm of intrinsic semiconductor materialadjacent to the charge compensation regions 846, an intermediate film of200 nm to 600 nm of n-type semiconductor having a dopant concentrationin a range of 2×10¹⁶ to 5×10¹⁶ atoms/cm³, and an inner film of 200 nm to600 nm of intrinsic semiconductor material. The buffer film helps toreduce mutual counter-doping between the charge compensation region 846and the intermediate film of the doped semiconductor layer 924. Theintermediate film is as thick as reasonable possible to provide highelectron mobility within the trenches 724.

An anisotropic etch is performed to remove portions of the dopedsemiconductor layer 924 overlying the hard mask layer 702 and along thebottoms of the trenches 724. The etch can be extended to recess thedoped semiconductor layer 924 such that the highest elevation of thedoped semiconductor layer 924 is 400 nm to 800 nm below an elevation ofthe tops of the pillars 722 (excluding the hard mask layer 702 thatoverlies the pillars 722). The recess etch forms the shoulder of thedoped semiconductor layer 924. Subsequently-formed gate electrodes forthe power transistor will be formed adjacent to the recesses. The hardmask layer 702 can be removed at this point in the process.

In a finished device, charge compensation regions 846 are p-type andelectrically connected to a subsequently-formed source electrode for thepower transistor adjacent to the top surface of the pillars 722, and thedoped semiconductor layer 924 is n-type and coupled to the substrate302. Thus, the doped semiconductor layer 924 is the drift region for thepower transistor, and the substrate 302 will be electrically connectedto a drain terminal for the power transistor.

FIGS. 11 and 12 include cross-sectional views of the full height of thestructure and an enlarged view near the top of the structure afterforming a gate dielectric layer 1102, a trench fill material 1104, gateelectrodes 1128, and body regions 1146. The gate dielectric layer 1102can be formed within the trenches 724 and over the pillars 722 (notlabeled in FIGS. 11 and 12). The gate dielectric layer 1102 can have athickness in a range of 30 nm to 150 nm. If needed or desired, a nitridefilm can be formed to protect the gate dielectric layer 1102 duringsubsequent processing. If the gate dielectric layer 1102 is formed at alater point in the process, the nitride film may not be formed. A trenchfill material 1104 is deposited over the gate dielectric layer 1102. Inan embodiment, the trench fill material 1104 can completely fill thetrenches 724 or be deposited to seal off the trenches 724 and form voidswithin the trenches 724. In an embodiment, the trench fill material 1104can be an insulator and include an oxide, a nitride, an oxynitride, andmay include a single film or a plurality of films.

In an embodiment, the trench fill material 1104 does not completely fillthe trenches 724 and leaves recessions along the surface. The recessionscan be filled with a semiconductor material or insulating material. Alayer of sufficient thickness is deposited along the exposed surface ofthe workpiece and fills in the recessions. Further processing of suchlayer can depend on the material of the layer and whether islands of thelayer are to remain within the trenches 724. In an embodiment, the layerincludes a semiconductor material and semiconductor islands are formed.A planarization operation is performed to remove the layer except withinthe recessions. An etch is performed to recess portions of the layerwithin the recessions to form the semiconductor islands. In anotherembodiment, the layer includes an insulating material. In a particularembodiment, a planarization operation is performed to remove portions ofthe layer and any trench fill material that overlies the pillars 722. Inthis embodiment, no semiconductor islands are formed.

An isotropic etch is performed to remove any remaining portion of thetrench fill material 1104 outside the trenches 724 and to removeportions of the trench fill material 1104 within the trenches 724. Whenthe trench fill material 1104 includes an oxide, and a nitride filmoverlies the gate dielectric layer 1102, the isotropic etch can beperformed with an oxide etchant that stops on the nitride film. In anembodiment in which semiconductor islands are formed, the isotropic etchmay be performed so that etch does not completely undercut thesemiconductor islands. The semiconductor islands may or may not beremoved at this point in the process. In an embodiment wheresemiconductor islands are not formed, undercut concerns are obviated.

The gate electrodes 1128 can be formed at this point in the process. Ifthe semiconductor islands are present, the semiconductor islands can bepart of the gate electrodes 1128. A heavily doped semiconductor layercan be formed over exposed portions of the workpiece, and portions ofthe heavily doped semiconductor layer can be removed by an etch-backprocess or planarization to form the gate electrodes 1128.

The body regions 1146 can be formed within the pillars 722 near theupper surface of the pillars 722. The body regions 1146 can be used tocontrol the threshold voltage of the power transistor structures. Thebody regions 1146 have a conductivity type opposite that of thesubstrate 302. Dopant for the body regions 1146 can be implanted using asingle implant or a sequence of different implants at differentenergies. The body regions 1146 can include a p-type dopant and have amaximum doping concentration in a range of 5×10¹⁵ to 5×10¹⁶ atoms/cm³,and a depth in a range of 0.3 micron to 1.2 microns. The actualconcentration and depth may depend on the device design, nominaloperating voltage, threshold voltage, drain-to-source breakdown voltage,or the like.

Source regions 1322 are formed, as illustrated in FIGS. 13 and 14. Thesource regions 1322 have the same conductivity type as the substrate302. In an embodiment, the source regions 1322 can include an n-typedopant and have a dopant concentration greater than 1×10¹⁹ atoms/cm³.The gate electrodes 1128 can be partly recessed to reduce source-to-gatecapacitance, if needed or desired.

Supplemental information and other alternatives regarding the trenchfill, gate electrode, body region, and source region formation aredisclosed in U.S. Pat. No. 9,620,585, which is incorporated by referencewith respect to structures within the active region and their formation.

FIGS. 15 and 16 illustrate a substantially completed physical structurethat corresponds to the circuit illustrated in FIGS. 1 and 2. Aninterlevel dielectric (ILD) layer 1502 is formed and patterned to definecontact openings 1504. The ILD layer 1502 can include one or more filmsof oxide, nitride, or oxynitride, and such films may be doped orundoped. The ILD layer 1502 can be formed by chemical or vapor phasedeposition. A mask is formed over the ILD layer 1502 and definesopenings that expose portions of the ILD layer 1502 where the contactopenings 1504 are formed. An etch is performed to etch through the ILDlayer 1502, the source regions 1322, and the body regions 1146. Bodycontact regions 1526 can be formed along the bottoms of the contactopenings 1504. The body contact regions 1526 are heavily doped and keptas shallow as reasonably possible. The mask is removed.

A metal layer is deposited and patterned to from a source electrode1542, and a gate terminal (not illustrated) electrically connected tothe gate electrodes 1128. The metal layer may include one or more filmsthat can include an adhesion film, a barrier film, and a bulk film thatmakes up most of the metal layer.

A passivation layer (not illustrated) is formed over the ILD layer 1502,the source electrode 1542, and the gate terminal. The passivation caninclude one or more films of an insulating material. In a particularembodiment, the passivation layer include polyimide that is coated andpattern to expose portions of the source electrode 1542 and the gateterminal. The reverse side of the semiconductor die may then be providedwith a drain electrode that contacts the substrate 302.

The semiconductor die with the structures seen in the figures can be putinto a package, and the packaged die may be mounted on a circuit orprinted wiring board. Thus, the electronic device can be thesemiconductor die, the packaged die, the circuit or printed wiringboard, at a higher level within an apparatus, or the like

The embodiments described above address n-channel FET structures. Forp-channel FET structures, opposite dopant types can be used. Inembodiments described above, the semiconductor material can be silicon.In other embodiment, other semiconductor materials, such as siliconcarbide, germanium, Group 13-Group 15, or other materials capable offorming a rectifying junction can be used. The actual dopants used maydepend on the principal compound making up the semiconductor material.

Embodiments as described herein can reduce the amount of ringing whenthe power transistor is switched off. FIG. 17 includes an illustrationof a comparison device 1700 that includes a power transistor without aring suppression structure. FIG. 17 further includes a simulation ofvoltage and current as a function of time during the reverse recovery ofthe body diode of the power transistor. In the simulations, the forwardbias body current was 10 A, and the reverse bias voltage was 100 V witha current ramp rate of 100 A per microsecond. The reverse recoverybegins at 100 nanoseconds when the forward current is zero and ends whenthe current returns to zero by about 170 nanoseconds. The peak reversecurrent occurs just after 160 nanoseconds. FIG. 18 includes a simulationof voltage and current as a function of time for a new power transistorthat includes transistors structures as described and illustrated withrespect to FIGS. 1 to 16. The simulation conditions were the same aspreviously described with respect to FIG. 17. There is less voltage andcurrent ringing in the device with the ring suppression structure. Also,the magnitude of the voltage and current overshoot/undershoot is greatlyreduced. Although the gate of the power transistor was not activatedduring the body diode reverse recovery simulations, similar results areobtained for switching events when the power transistor gate isactivated, such as occur in hard switching power conversion topologies.

Many different aspects and embodiments are possible. Some of thoseaspects and embodiments are described below. After reading thisspecification, skilled artisans will appreciate that those aspects andembodiments are only illustrative and do not limit the scope of thepresent invention. Embodiments may be in accordance with any one or moreof the embodiments as listed below.

Embodiment 1. A circuit including:

-   -   a first field-effect transistor having a body and a drain; and    -   a bipolar transistor having a base and a collector,    -   wherein:        -   the collector of the bipolar transistor is coupled to the            body of the first field-effect transistor; and        -   the drain of the first field-effect transistor is coupled to            the base of the bipolar transistor.

Embodiment 2. The circuit of Embodiment 1, further including a firstpower supply terminal coupled to the drain of the first field-effecttransistor; and a second power supply terminal coupled to a source ofthe first field-effect transistor.

Embodiment 3. The circuit of Embodiment 2, further including a secondfield-effect transistor having a gate, wherein the gate of the secondfield-effect transistor and the base of the bipolar transistor arecoupled to the first power supply terminal.

Embodiment 4. The circuit of Embodiment 3, further including a firstcharge storage element having a first electrode coupled to the firstpower supply terminal, and a second electrode coupled to a source of thesecond field-effect transistor.

Embodiment 5. The circuit of Embodiment 4, wherein the first chargestorage element is a first diode having an anode and a cathode, whereinthe cathode is coupled to the first power supply terminal, and the anodeis coupled to the source of the second field-effect transistor.

Embodiment 6. The circuit of Embodiment 5, further including a thirdfield-effect transistor having a source and a drain, wherein the drainis coupled to the second power supply terminal; and a second chargestorage element having a first terminal coupled to the first powersupply terminal, and a second terminal coupled to the source of thethird field effect transistor.

Embodiment 7. The circuit of Embodiment 6, further including a firstresistor having a first terminal coupled to the source of the secondfield-effect transistor, and a second terminal coupled to the source ofthe third field-effect transistor.

Embodiment 8. The circuit of Embodiment 6, further including a firstresistor and a second resistor, wherein:

-   -   a first terminal of the first resistor is electrically connected        to the collector of the bipolar transistor, and the second        terminal of the first resistor is electrically connected to a        source of the first field-effect transistor; and    -   a first terminal of the second resistor is electrically        connected to the drain of the third field-effect transistor, and        the second terminal of the second resistor is electrically        connected to the source of the first field-effect transistor.

Embodiment 9. The circuit of Embodiment 6, wherein:

-   -   the first field-effect transistor is an enhancement-mode power,        n-channel insulated gate field-effect transistor;    -   the bipolar transistor is a PNP transistor;    -   each of the second and third transistors is a depletion-mode        p-channel junction field-effect transistor;    -   the first charge storage element is a first pn junction diode        having an anode and a cathode;    -   the second charge storage element is a second pn junction diode        having an anode and a cathode;    -   an emitter of the bipolar transistor is electrically connected        to a drain of the second field-effect transistor;    -   the base of the bipolar transistor, the gate of the second        field-effect transistor, a gate of the third field-effect        transistor, and the cathodes of the first and second pn junction        diodes are electrically connected to one another;    -   the source of the second field-effect transistor is electrically        connected to the anode of the first pn junction diode; and    -   the source of the third field-effect transistor is electrically        connected to the anode of the second pn junction diode.

Embodiment 10. A circuit including a first diode having an anode and acathode; and a first field-effect transistor having a source and a gate,wherein the source is coupled to the anode of the first diode, and thegate is coupled to the cathode of the first diode.

Embodiment 11. The circuit of Embodiment 10, further including a firstcircuit terminal, a second circuit terminal, and a resistor having afirst terminal and a second terminal, wherein the cathode of the firstdiode is coupled to the first circuit terminal, the first terminal ofthe resistor is coupled to a drain of the first field-effect transistor,and the second terminal of the resistor is coupled to the second circuitterminal.

Embodiment 12. The circuit of Embodiment 10, further including:

-   -   a second diode having an anode and a cathode;    -   a second field-effect transistor having a source, a gate, and a        drain; and    -   a bipolar transistor having an emitter, a base, and a collector,    -   wherein:        -   the cathodes of the first and second diodes, the gates of            the first and second field-effect transistors, and the base            of the bipolar transistor are electrically connected to one            another; and        -   the emitter of the bipolar transistor is electrically            connected to the source of the second field-effect            transistor.

Embodiment 13. An electronic device including:

-   -   a substrate including a semiconductor material;    -   a first trench;    -   a second trench spaced apart from the first trench; and    -   a ring suppression structure disposed between the first and        second trenches and including:        -   a first doped region overlying the substrate and having a            first conductivity type;        -   a second doped region overlying the first doped region and            having a second conductivity type opposite that of the first            conductivity type; and        -   a third doped region overlying the second doped region and            having the first conductivity type.

Embodiment 14. The electronic device of Embodiment 13, further includinga gate electrode of a field-effect transistor structure adjacent to thefirst doped region.

Embodiment 15. The electronic device of Embodiment 14, wherein the gateelectrode is closer to:

-   -   a bottom of the first trench than to a top of the first trench;    -   a bottom of the second trench than to a top of the second        trench; or    -   the bottoms of the first and second trenches than to the tops of        the first and second trenches.

Embodiment 16. The electronic device of Embodiment 13, wherein:

-   -   the first doped region includes a first portion, a second        portion, and a third portion;    -   the second portion of the first doped region is disposed between        and narrower than each of the first and third portions of the        first doped region; and    -   the second doped region is closer to the third portion of the        first doped region than to each of the first and second portions        of the first doped region.

Embodiment 17. The electronic device of Embodiment 16, wherein thesecond portion of the first doped region includes a pinch-off region ofa field-effect transistor structure.

Embodiment 18. The electronic device of Embodiment 17, further includinga gate electrode of the field-effect transistor structure adjacent tothe second portion of the first doped region.

Embodiment 19. The electronic device of Embodiment 13, wherein thesecond doped region is a base region of a bipolar transistor structure.

Embodiment 20. The electronic device of Embodiment 13, further includingan active field-effect transistor structure, wherein the activefield-effect transistor structure and the ring suppression structure aredisposed between the first and second trenches.

Embodiment 21. An electronic device including:

-   -   a first structure including:        -   a first doped region having a first conductivity type;        -   a second doped region overlying the first doped region and            having a second conductivity type opposite the first            conductivity type; and        -   a third doped region overlying the second doped region and            having the first conductivity type; and    -   a second structure including a fourth doped region having the        first conductivity type and coupled to the first doped region of        the first structure.

Embodiment 22. The electronic device of Embodiment 21, wherein thesecond doped region abuts each of the first and third doped regions, isa base region of a bipolar transistor structure, and is coupled to apower supply terminal.

Embodiment 23. The electronic device of Embodiment 21, wherein the thirdand fourth doped regions are coupled to a power supply terminal.

Embodiment 24. The electronic device of Embodiment 21, wherein the firststructure is a ring suppression structure, and the second structure is acontact structure coupled to the first doped region.

Note that not all of the activities described above in the generaldescription or the examples are required, that a portion of a specificactivity may not be required, and that one or more further activitiesmay be performed in addition to those described. Still further, theorder in which activities are listed is not necessarily the order inwhich they are performed.

Benefits, other advantages, and solutions to problems have beendescribed above with regard to specific embodiments. However, thebenefits, advantages, solutions to problems, and any feature(s) that maycause any benefit, advantage, or solution to occur or become morepronounced are not to be construed as a critical, required, or essentialfeature of any or all the claims.

The specification and illustrations of the embodiments described hereinare intended to provide a general understanding of the structure of thevarious embodiments. The specification and illustrations are notintended to serve as an exhaustive and comprehensive description of allof the elements and features of apparatus and systems that use thestructures or methods described herein. Separate embodiments may also beprovided in combination in a single embodiment, and conversely, variousfeatures that are, for brevity, described in the context of a singleembodiment, may also be provided separately or in any subcombination.Further, reference to values stated in ranges includes each and everyvalue within that range. Many other embodiments may be apparent toskilled artisans only after reading this specification. Otherembodiments may be used and derived from the disclosure, such that astructural substitution, logical substitution, or another change may bemade without departing from the scope of the disclosure. Accordingly,the disclosure is to be regarded as illustrative rather thanrestrictive.

What is claimed is:
 1. A circuit comprising: a first field-effect transistor having a body and a drain; and a bipolar transistor having a base and a collector, wherein: the collector of the bipolar transistor is coupled to the body of the first field-effect transistor, and the drain of the first field-effect transistor is coupled to the base of the bipolar transistor.
 2. The circuit of claim 1, further comprising: a first power supply terminal coupled to the drain of the first field-effect transistor; and a second power supply terminal coupled to a source of the first field-effect transistor.
 3. The circuit of claim 2, further comprising a second field-effect transistor having a gate, wherein the gate of the second field-effect transistor and the base of the bipolar transistor are coupled to the first power supply terminal.
 4. The circuit of claim 3, further comprising a first charge storage element having a first electrode coupled to the first power supply terminal, and a second electrode coupled to a source of the second field-effect transistor.
 5. The circuit of claim 4, wherein the first charge storage element is a first diode having an anode and a cathode, wherein the cathode is coupled to the first power supply terminal, and the anode is coupled to the source of the second field-effect transistor.
 6. The circuit of claim 4, further comprising: a third field-effect transistor having a source and a gate, wherein the gate is coupled to the first power supply terminal; and a second charge storage element having a first electrode coupled to the first power supply terminal, and a second electrode coupled to the source of the third field effect transistor.
 7. The circuit of claim 6, further comprising a first resistor having a first terminal coupled to the source of the second field-effect transistor, and a second terminal coupled to the source of the third field-effect transistor.
 8. The circuit of claim 6, further comprising: a fourth field-effect transistor having a source and a drain; a first resistor having a first terminal and a second terminal; and a second resistor having a first terminal and a second terminal, wherein: the drain of the fourth field-effect transistor and the gate of the third field-effect transistor are electrically connected to each other, the first terminal of the first resistor and the collector of the bipolar transistor are electrically connected to each other, the second terminal of the first resistor and the source of the first field-effect transistor are electrically connected to each other, the first terminal of the second resistor is electrically connected to a drain of the third field-effect transistor, and the second terminal of the second resistor is electrically connected to the source of the fourth field-effect transistor.
 9. The circuit of claim 6, wherein: the first field-effect transistor is an enhancement-mode power, n-channel insulated gate field-effect transistor, the bipolar transistor is a PNP transistor, the second and third transistors are depletion-mode p-channel junction field-effect transistors, the first and second charge storage elements are first and second pn junction diodes, each having an anode and a cathode, an emitter of the bipolar transistor and a drain of the second field-effect transistor are electrically connected to each other, the base of the bipolar transistor, the gate of the second field-effect transistor, the gate of the third field-effect transistor, and the cathodes of the first and second pn junction diodes are electrically connected to one another, the source of the second field-effect transistor and the anode of the first pn junction diode are electrically connected to each other, and the source of the third field-effect transistor and the anode of the second pn junction diode are electrically connected to each other.
 10. A circuit comprising: a first diode having an anode and a cathode; and a first field-effect transistor having a source and a gate, wherein the source is coupled to the anode of the first diode, and the gate is coupled to the cathode of the first diode.
 11. The circuit of claim 10, further comprising a first circuit terminal, a second circuit terminal, and a resistor having a first terminal and a second terminal, wherein the cathode of the first diode is coupled to the first circuit terminal, the first terminal of the resistor is coupled to a drain of the first field-effect transistor, and the second terminal of the resistor is coupled to the second circuit terminal.
 12. The circuit of claim 10, further comprising: a second diode having an anode and a cathode; a second field-effect transistor having a source, a gate, and a drain; and a bipolar transistor having an emitter, a base, and a collector, wherein: the cathodes of the first and second diodes, the gates of the first and second field-effect transistors, and the base of the bipolar transistor are electrically connected to one another, and the emitter of the bipolar transistor and the drain of the second field-effect transistor are electrically connected to each other.
 13. The circuit of claim 12, further comprising a third field-effect transistor having a source, a gate, and a drain; and a fourth field-effect transistor having a source, a gate, and a drain, wherein: the sources of the third and fourth field-effect transistors are electrically connected to each other, the gates of the third and fourth field-effect transistors are electrically connected to each other, the drain of the third field-effect transistor, the gate of the first field-effect transistor, and the cathode of the first diode are electrically connected to one another, and the drain of the fourth field-effect transistor, the base of the bipolar transistor, the gate of the second field-effect transistor, the cathode of the second diode are electrically connected to one another.
 14. The circuit of claim 13, further comprising: a first resistor having a first terminal and a second terminal; and a second resistor having a first terminal and a second terminal, wherein: the first terminal of the first resistor and a drain of the first field-effect transistor are electrically connected to each other, the second terminal of the first resistor and the source of the third field-effect transistor are electrically connected to each other, the first terminal of the second resistor and the collector of the bipolar transistor are electrically connected to each other, and the second terminal of the second resistor and the source of the fourth field-effect transistor are electrically connected to each other.
 15. The circuit of claim 14, wherein: the first and second transistors are depletion-mode p-channel junction field-effect transistors, the third and fourth field-effect transistors are enhancement-mode power, n-channel insulated gate field-effect transistors, and the bipolar transistor is a PNP transistor.
 16. A circuit comprising: a ring suppression portion including a first insulated-gate field-effect transistor having a source, a gate, and a drain; and a contact portion including a second insulated-gate field-effect transistor having a source, a gate, and a drain, wherein: (1) the sources of the first and second insulated-gate field-effect transistors are coupled to each other, (2) the gates of the first and second insulated-gate field-effect transistors are coupled to each other, (3) the drains of the first and second insulated-gate field-effect transistors are coupled to each other, or any combination of (1), (2), and (3).
 17. The circuit of claim 16, further comprising a bipolar transistor including a base that is coupled to the drain of the first insulated-gate field-effect transistor.
 18. The circuit of claim 17, further comprising: a first junction field-effect transistor having a source, a gate, and a drain; and a second junction field-effect transistor having a source, a gate, and a drain, wherein: the drain of the first junction field-effect transistor and an emitter of the bipolar transistor are electrically connected to each other, the gates of the first and second junction field-effect transistors are electrically connected to one another, the drain of the second junction field-effect transistor is coupled to the source of the second insulated-gate field-effect transistor.
 19. The circuit of claim 18, further comprising: a first charge storage element having a first electrode and a second electrode; and a second charge storage element having a first electrode and a second electrode, wherein: the first electrodes of the first and second charge storage elements are coupled to the drains of the first and second insulated-gate field-effect transistors, the second electrode of the first charge storage element is coupled to the source of the first junction field-effect transistor, and the second electrode of the second charge storage element is coupled to the source of the second junction field-effect transistor.
 20. The circuit of claim 19, wherein: the ring suppression portion further includes the bipolar transistor, the first junction field-effect transistor, and the first charge storage element, the contact portion further includes the second junction field-effect transistor and the second charge storage element, the first and second field-effect transistors are enhancement-mode, n-channel insulated gate field-effect transistors, the bipolar transistor is a PNP transistor, the first and second junction field-effect transistors are depletion-mode p-channel junction field-effect transistors, the first and second charge storage elements are first and second pn junction diodes, respectively, the first electrodes are cathodes, and the second electrodes are anodes, the sources of the first and second insulated-gate field-effect transistors are electrically connected to each other, the gates of the first and second insulated-gate field-effect transistors are electrically connected to each other, the drains of the first and second insulated-gate field effect transistors, the base of the bipolar transistor, the gates of the first and second junction field-effect transistors, and the cathodes of the pn junction diodes are electrically connected to one another, the source of the first junction field-effect transistor and the anode of the first pn junction diode are electrically connected to each other, and the source of the second junction field-effect transistor and the anode of the second pn junction diode are electrically connected to each other. 